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Add "buffered-normalized mode", add $buf cell type, and add "bufnorm" command #3967

Merged
merged 11 commits into from
Sep 17, 2024
Merged

Add "buffered-normalized mode", add $buf cell type, and add "bufnorm" command #3967

merged 11 commits into from
Sep 17, 2024

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clairexen
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This PR adds "buffered-normalized mode" to RTLIL. In that mode there's a 1:1 relationship between cell ouput ports and wires, and each wire is annotated with a reference to the cell and cell port driving it.

Once in "buffered-normalized mode" calling design->bufNormalize() (or module->bufNormalize()) will ensure that the above condition is met, by adding additional intermediate wires and buffer cells as needed.

This PR also adds a $buf "coarse-grain" buffer cell type, similar in behavior to $pos, but techmap/simplemap/etc is not mapping this buffer type to an array of single-bit buffers. bufNormalize() is adding buffers of that new $buf type. Note that bufNormalize() is very efficient and only looks at the parts of the design that have been changed since the last time bufNormalize() has been run, i.e. it does not require a complete scan over the design.

This PR also adds the bufnorm command for getting the design into and out of "buffered-normalized mode", with more control over the exact type of network of buffers that is being created.

@clairexen clairexen marked this pull request as draft September 29, 2023 14:10
@povik
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povik commented Oct 16, 2023

This PR also adds a $buf "coarse-grain" buffer cell type, similar in behavior to $pos, but techmap/simplemap/etc is not mapping this buffer type to an array of single-bit buffers.

FWIW that doesn't seem to be the behavior for $pos cells either

yosys/passes/techmap/simplemap.cc

Lines 45 to 53 in 7d30f71

void simplemap_pos(RTLIL::Module *module, RTLIL::Cell *cell)
{
RTLIL::SigSpec sig_a = cell->getPort(ID::A);
RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
sig_a.extend_u0(GetSize(sig_y), cell->parameters.at(ID::A_SIGNED).as_bool());
module->connect(RTLIL::SigSig(sig_y, sig_a));
}

@widlarizer
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widlarizer commented Jun 5, 2024 •
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Since setPort may bufNormQueue.insert, a Cell* may survive in bufNormQueue beyond when the underlying cell is removed. Repro: rebase this branch onto main (855ac28), then read_rtlil bug.proc.il; bufnorm -update; opt; bufnorm -update segfaults on my linux machine, where bug.proc.il is

autoidx 16

module \bug

  wire width 32 $procmux$14_Y

  wire $procmux$15_CMP

  wire $auto$bugpoint.cc:258:simplify_something$1

  wire width 32 output 1 $auto$bugpoint.cc:258:simplify_something$3

  wire width 30 $auto$bugpoint.cc:258:simplify_something$4

  wire width 32 $auto$bugpoint.cc:258:simplify_something$5

  wire $delete_wire$6

  wire width 32 \pc$next

  cell $mux $procmux$14
    parameter \WIDTH 32
    connect \Y $procmux$14_Y
    connect \S $procmux$15_CMP
    connect \B 0
    connect \A 32'x
  end

  cell $dff $7
    parameter \WIDTH 32
    parameter \CLK_POLARITY 1
    connect \Q $auto$bugpoint.cc:258:simplify_something$3
    connect \D \pc$next
    connect \CLK $auto$bugpoint.cc:258:simplify_something$1
  end

  connect $procmux$15_CMP $delete_wire$6
  connect \pc$next $procmux$14_Y
end

@whitequark
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oh hey, a new user of bugpoint :D

@povik povik mentioned this pull request Jun 17, 2024
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@povik povik mentioned this pull request Sep 10, 2024
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povik approved these changes Sep 11, 2024
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Apart from the bufnorm command (which I haven't reviewed so I at least marked it experimental) this looks good to me. There are some outstanding issues (e.g. what Emil points out) but they don't affect all use cases. I am in favor of merging this as is to get the ball moving

@povik povik added the merge-after-jf Merge: PR will be merged after the next Dev JF unless concerns are raised label Sep 11, 2024
@povik povik marked this pull request as ready for review September 11, 2024 10:20
clairexen and others added 11 commits September 17, 2024 10:46
@clairexen @povik
Add bufnorm pass
d0b5dfa 
Signed-off-by: Claire Xenia Wolf <[email protected]>
@clairexen @povik
Improvements and fixes to "bufnorm" cmd
32808a0 
Signed-off-by: Claire Xenia Wolf <[email protected]>
@clairexen @povik
Improvements in "bufnorm" pass
f4b7ea5 
Signed-off-by: Claire Xenia Wolf <[email protected]>
@clairexen @povik
Add coarse-grain $buf buffer cell type
4d469f4 
Signed-off-by: Claire Xenia Wolf <[email protected]>
@clairexen @povik
Improvements in "bufnorm" pass
d027ead 
Signed-off-by: Claire Xenia Wolf <[email protected]>
@clairexen @povik
Improvements in "bufnorm" pass
8bb70ba 
Signed-off-by: Claire Xenia Wolf <[email protected]>
@clairexen @povik
Add RTLIL "buffered-normalized mode" and improve "bufnorm" pass
8011938 
Signed-off-by: Claire Xenia Wolf <[email protected]>
@povik
Adjust buf-normalized mode
865df26
@povik
Mark bufnorm experimental
38de018
@povik
dump: Update help after option removal
e13ace6
@povik
simlib: Add $buf disclaimer
eeffca9
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povik commented Sep 17, 2024

Rebased to pull in updated CI

@povik povik merged commit a553b7c into main Sep 17, 2024
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@povik povik deleted the claire/bufnorm branch September 17, 2024 09:27
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@clairexen @povik @widlarizer @whitequark